base_system Project Status (10/14/2015 - 12:48:04)
Project File: axi_timer_test.xise Parser Errors: No Errors
Module Name: base_system_top Implementation State: Programming File Generated
Target Device: xc6slx9-2csg324
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
104 Warnings (1 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
XPS Reports [-]
Report NameGenerated ErrorsWarningsInfos
Platgen Log File水 10 14 12:36:08 201501 Warning (1 new)11 Infos (0 new)
Simgen Log File    
BitInit Log File水 10 14 12:48:03 20150011 Infos (0 new)
System Log File    
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 2,787 11,440 24%  
    Number used as Flip Flops 2,779      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 8      
Number of Slice LUTs 3,410 5,720 59%  
    Number used as logic 3,111 5,720 54%  
        Number using O6 output only 2,393      
        Number using O5 output only 56      
        Number using O5 and O6 662      
        Number used as ROM 0      
    Number used as Memory 214 1,440 14%  
        Number used as Dual Port RAM 88      
            Number using O6 output only 4      
            Number using O5 output only 0      
            Number using O5 and O6 84      
        Number used as Single Port RAM 0      
        Number used as Shift Register 126      
            Number using O6 output only 36      
            Number using O5 output only 1      
            Number using O5 and O6 89      
    Number used exclusively as route-thrus 85      
        Number with same-slice register load 79      
        Number with same-slice carry load 6      
        Number with other load 0      
Number of occupied Slices 1,319 1,430 92%  
Number of MUXCYs used 528 2,860 18%  
Number of LUT Flip Flop pairs used 3,957      
    Number with an unused Flip Flop 1,409 3,957 35%  
    Number with an unused LUT 547 3,957 13%  
    Number of fully used LUT-FF pairs 2,001 3,957 50%  
    Number of unique control sets 234      
    Number of slice register sites lost
        to control set restrictions
954 11,440 8%  
Number of bonded IOBs 54 200 27%  
    Number of LOCed IOBs 54 54 100%  
Number of RAMB16BWERs 14 32 43%  
Number of RAMB8BWERs 0 64 0%  
Number of BUFIO2/BUFIO2_2CLKs 1 32 3%  
    Number used as BUFIO2s 1      
    Number used as BUFIO2_2CLKs 0      
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 3 16 18%  
    Number used as BUFGs 3      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 0 200 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 23 200 11%  
    Number used as IODELAY2s 0      
    Number used as IODRP2s 1      
    Number used as IODRP2_MCBs 22      
Number of OLOGIC2/OSERDES2s 43 200 21%  
    Number used as OLOGIC2s 0      
    Number used as OSERDES2s 43      
Number of BSCANs 1 4 25%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 1 4 25%  
Number of DSP48A1s 3 16 18%  
Number of ICAPs 0 1 0%  
Number of MCBs 1 2 50%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 1 2 50%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 3.90      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent水 10 14 12:44:22 20150061 Infos (0 new)
Translation ReportCurrent水 10 14 12:45:22 2015030 Warnings (1 new)5 Infos (4 new)
Map ReportCurrent水 10 14 12:46:44 2015024 Warnings (0 new)10 Infos (1 new)
Place and Route ReportCurrent水 10 14 12:47:19 2015026 Warnings (0 new)2 Infos (1 new)
Power Report     
Post-PAR Static Timing ReportCurrent水 10 14 12:47:31 201501 Warning (0 new)4 Infos (1 new)
Bitgen ReportCurrent水 10 14 12:47:54 2015023 Warnings (0 new)0
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk Log FileCurrent水 10 14 12:47:54 2015

Date Generated: 10/14/2015 - 12:48:04