base_system Project Status (10/14/2015 - 12:48:04) | |||
Project File: | axi_timer_test.xise | Parser Errors: | No Errors |
Module Name: | base_system | Implementation State: | Programming File Not Generated |
Target Device: | xc6slx9-2csg324 |
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Product Version: | ISE 14.7 |
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Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: |
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XPS Reports | [-] | ||||
Report Name | Generated | Errors | Warnings | Infos | |
Platgen Log File | 10 14 12:36:08 2015 | 0 | 1 Warning (1 new) | 11 Infos (0 new) | |
Simgen Log File | |||||
BitInit Log File | 10 14 12:48:03 2015 | 0 | 0 | 11 Infos (0 new) | |
System Log File |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | ||||||
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
CPLD Fitter Report (Text) | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
WebTalk Log File | Current | 10 14 12:47:54 2015 |